1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a function to inspect the connection states of bonding wires between pads of the chip of the integrated circuit and external terminals of a package housing the chip.
2. Description of the Related Background Art
A semiconductor integrated circuit comprises an integrated circuit chip made of a semiconductor or the like having an integrated circuit formed thereon and a package housing the integrated circuit chip. A plurality of pads for input from/output to the outside such as power supply pads, ground pads, and signal pads are formed on the integrated circuit chip and connected by bonding wires to external terminals, called leads or pins, provided in the package housing the integrated circuit chip. With these bonding wires, a bonding failure may occur where a bonding wire is debonded to be open or is shorted to an adjacent external terminal depending on the wire connection state resulting from the bonding process of semiconductor integrated circuit manufacturing. In order to deal with the bonding failure, semiconductor integrated circuits are usually inspected for bonding failures in a test process.
As semiconductor integrated circuits become larger in scale, more external terminals are formed in the semiconductor integrated circuit, and hence a test circuit is formed therein to efficiently determine the occurrence of a bonding failure with a wire between an external terminal and a pad for each external terminal (see Japanese Patent Application Laid-Open Publications No. H05-275621 (hereinafter called Reference 1), No. H11-237441, and No. 2000-193709).
FIG. 1 shows a test circuit for a semiconductor integrated circuit shown in Reference 1, and FIG. 2 shows a time chart for the circuit of FIG. 1. In the test circuit, when a first logical pattern of 0, 1, 0, and 1 is input to external terminals S1, S2, S3, and S4 to be inspected for a bonding failure, if all the external terminals S1, S2, S3, and S4 have a wire normally bonded thereto, all PMOS transistors P1, P2, P3, and P4 become ON, and thus a high level of a power supply voltage Vdd is transmitted to a node M. Hence 1 is latched into a latch circuit 3. Meanwhile, at this time all NMOS transistors N1, N2, N3, and N4 become OFF, and thus a node N becomes a high level of the power supply voltage Vdd which corresponds to logic n “1” because of the operation of a pull-up circuit. Hence 0 is latched into a latch circuit 4. Therefore an AND circuit 5 for outputting an STM signal that indicates a test result outputs the STM signal of zero regardless of an external test start signal ST. When a second logical pattern of 1, 0, 1, and 0 that is the opposite of the first logical pattern is subsequently input to the external terminals S1, S2, S3, and S4, the NMOS transistors N1, N2, N3, and N4 become ON, so that the node N becomes a ground level which corresponds to logic “0”, and thus a zero is input to an inverter 6 and its inverted output of “1” is latched into the latch circuit 4. The PMOS transistors P1, P2, P3, and P4 become OFF, and thus the node M becomes the ground level because of the operation of a pull-down circuit 1. However, because an SR signal=“L”, the latched value of the latch circuit 3 does not change but remains “1”. Because the ST signal is at “1”, the STM signal, which is the output signal, becomes “1”. Therefore, if the external terminals S1, S2, S3, and S4 have a wire normally bonded thereto, as a result of inputting the two patterns, the STM signal becomes “1”. On the other hand, in a bonding failure case where any of the external terminals S1, S2, S3, and S4 has a wire not normally bonded thereto, one or more of the PMOS transistors P1, P2, P3, P4 and the NMOS transistors N1, N2, N3, N4 do not become ON. Hence for the first logical pattern, the level on the node M is pulled down to “0”, so that “0” is latched into the latch circuit 3, and for the second logical pattern, the level on the node N is pulled up to “1” by the pull-up circuit 2, so that the inverted output of “0” is latched into the latch circuit 4. In this case, as a result of inputting the two patterns, the STM signal becomes “0”. The semiconductor integrated circuit can be determined to be good when the STM signal=“1” as a result of inputting the two patterns and to be defective in bonding when the STM signal=“0”.
In the above conventional test circuit, an external-terminal open/short state in the integrated circuit can be realized by inputting a predetermined terminal check control signal to the external terminals, and only when normal, the STM signal becomes “1”, thus producing the effect of reducing terminal test time for semiconductor integrated circuits with multiple external terminals. However, because the terminal check control signal of the two patterns has to be input, there is the drawback that the test sequence is complex. Furthermore, in LSIs (large scale integrated circuits) such as memories, particular pads thereof may be connected to power supply terminals or ground terminals of external terminals to fix an operation mode, in manufacturing. For the logically-fixed pads whose potentials are fixed, two patterns cannot be input in test as above, and hence there is a problem in that correct inspection cannot be performed in the conventional test circuit.